TUM Logo

Design and Implementation of flexible Hardware Support for Memory Safety in RISC-V inside the gem5 Simulator

Design and Implementation of flexible Hardware Support for Memory Safety in RISC-V inside the gem5 Simulator

Supervisor(s): Konrad Hohentanner, Lukas Auer
Status: inprogress
Topic: Others
Author: Lukas Hertel
Submission: 2023-08-15
Type of Thesis: Bachelorthesis
Thesis topic in co-operation with the Fraunhofer Institute for Applied and Integrated Security AISEC, Garching

Description