Enabling Hardware-Accelerated Fault-Tolerant Memory Safety on RISC-V
Enabling Hardware-Accelerated Fault-Tolerant Memory Safety on RISC-V
| Supervisor(s): | Lukas Auer, Benjamin Orthen, Dr. Julian Horsch |
| Status: | inprogress |
| Topic: | Others |
| Author: | Raffaele Tranquillini |
| Submission: | 2024-02-15 |
| Type of Thesis: | Masterthesis |
Thesis topic in co-operation with the Fraunhofer Institute for Applied and Integrated Security AISEC, Garching
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Description |
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