Simulation and Analysis of Fault Injection focusing on the difference through the Instruction Set Architecture

Fault injection has become a powerful tool in the hardware security domain for testing system vulnerability to ensure data

integrity and information confidentiality. Fault injection involves inducing faults into a system to alter data or execution and

exploiting that system using the induced faults. This behavior enables the identification of potential vulnerabilities and the

implementation of appropriate countermeasures to mitigate potential attacks.

Fault injection, however, bears the disadvantage that expensive experimental setups are required. As part of this thesis, a Fault

Injection Tool for Analysis and Simulation (FITAS) was developed and implemented to facilitate fault injection. By using FITAS and

extracting working fault models from scientific papers, these expensive experimental setups can be avoided.

Several scientific papers have been published in which fault injection has been tested and analyzed on a variety of processors.

The aim of this thesis is to simulate the conduction of fault injection on two specific instruction set architectures on the instruction

set level. For this purpose, FITAS provides the capability to induce faults in opcodes of instructions from the ARM Cortex-M0 as well as

RISC-V instruction set architecture. The results of these manipulations are visualized through various plots enabling a comparison between

the different instruction sets, an assumption about the presumed general structure of an instruction's opcode, and a determination of the

effectiveness the extracted fault models have on both instruction sets. Additionally, an overview of the essential fault injection methodologies

is given. Finally, suggestions for extending FITAS are presented, since some functionalities are currently not integrated and further instruction

sets can be added.